Current deep sub-micron CMOS processes use four photolithography steps to form proper source/drain (S/D) junctions having lightly doped drain (LDD) junctions, and to produce desired transistor characteristics.
FIG. 1 shows a cross-sectional view of a semiconductor substrate 10 in an intermediate stage of a standard deep sub-micron CMOS process. Substrate 10 is shown with isolation regions 15, a gate oxide layer 20 on the surface of substrate 10, and polysilicon gates 25. A photoresist layer 30 is patterned over a N- well 35 and a masked N- implant is ther performed, creating self-aligned NLDD junctions 40. A P- implant is also performed creating halo regions 45. Photoresist layer 30 is then removed and a thermal cycle drives in the N- implant and the P- implant. A second photoresist layer 50 is then patterned over substrate 10, as shown in FIG. 2. A masked P- implant is performed creating self-aligned PLDD junctions 55.
FIG. 3 shows spacer sidewalls 60 formed on polysilicon gates 25 after gate oxide 20 has been removed. A third photoresist layer 65 is patterned over N- well region 35. A masked arsenic N+ implant is performed forming source/drain junctions 70. Photoresist layer 65 is removed and an annealing thermal cycle is used to drive in the N+ implant.
FIG. 4 shows a fourth photoresist layer 75 patterned into a mask. A masked P+ implant is then performed forming source/drain junctions 80. Photoresist layer 75 is then removed and an annealing thermal cycle drives in the P+ implant.
Thus, as illustrated in FIGS. 1-4, there are four photolithography steps to produce source/drain junctions with LDDs in standard CMOS processing. Each photolithography step, however, is costly and time consuming because of the materials used and the reduction in throughput. Therefore, a method to limit the amount of required photolithography steps is desirable.